An input buffer is a gate that receives an input signal and isolates the input signal from a load. The input buffer may also restore the logic levels of the input signal, increase input signal margins, provide increased driving capability, and provide better noise immunity. An input buffer circuit in a integrated circuit, such as an integrated circuit memory, is used to buffer, for example, address signals, control signals, and data signals.
An input buffer must operate within a specified power supply voltage range, such as 3.3 volt.+-.5%. Set-up and hold times for an address signal in an integrated circuit memory must be within specified parameters for the entire operating power supply voltage range. For example, the margins of an input buffer may be adversely affected if the power supply voltage varies from the designed power supply voltage range.
FIG. 1 illustrates, in partial schematic diagram form and partial logic diagram form, input buffer 10 in accordance with the prior art. Input buffer 10 includes first stages 12 and 14, and second stages 16 and 18. First stage 12 includes inverter 19, P-channel transistors 20, 22, and 23, NPN bipolar transistor 24, and N-channel transistor 25. Inverter 19 includes P-channel transistor 20 and N-channel transistor 21. First stage 14 includes inverter 26, P-channel transistors 27, 29, and 30, NPN bipolar transistor 31, and N-channel transistor 32. Inverter 26 includes P-channel transistor 27 and N-channel transistor 28. Second stage 16 includes inverter 34, P-channel transistor 36, NPN bipolar transistor 35, and N-channel transistor 37. Second stage 18 includes inverters 39, 42, and 46, NPN bipolar transistors 40 and 44, P-channel transistor 43, and N-channel transistors 41 and 45. Input buffer 10 receives a single-ended input signal, and in response, provides buffered differential signals, labeled "OUT" and "OUT.sup.* ", corresponding to the input signal. Buffered differential signals OUT and OUT.sup.* may then be provided as input signals to other circuitry on the integrated circuit. Note that an asterisk (.sup.*) after a signal name indicates that the signal is a logical complement of a signal having the same name but lacking the asterisk (.sup.*). Input buffer 10 receives a power supply voltage through power supply voltage terminals labeled "V.sub.DD ", and power supply voltage terminus labeled "V.sub.SS ". The power supply voltage may vary from the specified voltage for various reasons.
The operation of input buffer 10 will be described with reference to FIG. 2 and FIG. 3. FIG. 2 illustrates a waveform of the transient response of input buffer 10 of FIG. 1 for relatively low and relatively high power supply voltage levels. FIG. 3 illustrates a waveform of the DC response of input buffer 10 of FIG. 1 for the relatively low and relatively high power supply voltage levels. For purposes of discussion, the DC response is defined as the output signal response when the input signal transitions relatively slowly from one logic state to another. The transient response is defined as the output signal response when the input signal transitions within the target specification.
During normal operation of input buffer 10, an input signal labeled "IN" is provided to the gates of P-channel transistor 20 and N-channel transistor 21 of first stage 12 and the gates of P-channel transistor 27 and N-channel transistor 28 of first stage 14. As illustrated in FIG. 2, input signal IN transitions from a logic high voltage equal to about 3.0 volts to a logic low voltage equal to about zero volts. In order for a P-channel transistor to become conductive, its gate-to-source voltage (V.sub.GS) must be more negative than the threshold voltage of the P-channel transistor. An N-channel transistor becomes conductive when its V.sub.GS is more positive than the threshold voltage of the N-channel transistor. P-channel transistors 213 and 27 go from being substantially non-conductive to being conductive as the voltage of input signal IN decreases below the threshold voltage of P-channel transistors 20 and 27. Also, N-channel transistors 21 and 28 go from being conductive to being substantially non-conductive as the voltage of input signal IN decreases below the threshold voltage of N-channel transistors 2i and 28. If the power supply voltage changes, the voltage of input signal IN which causes P-channel transistors 20 and 27 to become conductive changes because the V.sub.GS of P-channel transistors 20 and 27 changes with the power supply voltage. To illustrate this, FIG. 2 and FIG. 3 illustrate differential output signals OUT and OUT.sup.* at both a relatively high power supply voltage (about 3.5 volts) and at a relatively low power supply voltage (about 3.0 volts). In FIG. 2, differential output signals OUT and OUT.sup.* at the lower power supply voltage require more time to change logic states, in part because the V.sub.GS of P-channel transistors 20 and 27 is lower. Input signal IN must therefore be lower for the P-channel transistors to go from being non-conductive to conductive. Referring to FIG. 3, for the lower power supply voltage, differential output signals OUT/OUT.sup.* transition at a lower voltage level of input signal IN than the differential output signals OUT and OUT.sup.* of the high power supply voltage, thus increasing the range of output signal transitions for a varying power supply voltage.
If input buffer 10 is used as, for example, an address buffer in an integrated circuit memory, the address set-up and hold margins must be relatively large to account for changes in the power supply voltage. The larger set-up and hold margins limit the speed at which the integrated circuit memory can operate.